states bitweise definieren
constant s0 : std_logic_vector(2 downto 0) := "000"; constant s1 : std_logic_vector(2 downto 0) := "100"; constant s2 : std_logic_vector(2 downto 0) := "110"; constant s3 : std_logic_vector(2 downto 0) := "011"; constant s4 : std_logic_vector(2 downto 0) := "001"; constant s5 : std_logic_vector(2 downto 0) := "111"; signal state : std_logic_vector(2 downto 0); signal next_state: std_logic_vector(2 downto 0);
states als type
type actual_state is (s0, s1, s2, s3, s4, s5, s6, s7);
signal state: actual_state := s0;
signal next_state: actual_state ;
Enumeriter Type
type actual_state is (s0, s1, s2, s3); attribute enum_encoding : string; attribute enum_encoding of actual_state: type is "00 01 10 11"; // nicht sicher: signal state: actual_state := s0; signal next_state: actual_state ;
State-Zuweisung
fsm: process (all)
begin
if (KEY_1 = '0') then
state <= s0;
elsif (rising_edge(CLOCK_27)) then
state <= next_state;
end if;
end process;
Logik Events
fsm_input: process (all)
begin
case state is
when s0 =>
if(pulse ='1') then
next_state <= s1;
else
next_state <= s0;
end if;
when s1 =>
if(pulse ='1') then
if SW_17 = '1' the
next_state <= s2;
else
next_state <= s0;
end if;
else
next_state <= s1;
end if;
when s2 => next_state <= s3;
when s3 => next_state <= s4;
when s4 => next_state <= s5;
when s5 => next_state <= s6;
when s6 => next_state <= s7
when s7 => next_state <= s7;
end case;
end process;
Output Action
fsm_output: process (all)
begin
case state is
when s0 => out <= "001";
when s1 => out <= "011"; GPIO_0_0 <= '1';
when s2 => LEDR_2 <= '1';
when s3 => LEDR_3 <= '1';
when OTHERS => NULL;
end case;
end process;
