{"id":151,"date":"2015-09-18T12:11:32","date_gmt":"2015-09-18T12:11:32","guid":{"rendered":"http:\/\/coolt.ch\/notizen\/?p=151"},"modified":"2015-10-28T09:06:28","modified_gmt":"2015-10-28T09:06:28","slug":"vhdl-projekt-erstellen","status":"publish","type":"post","link":"https:\/\/coolt.ch\/notizen\/vhdl-projekt-erstellen\/","title":{"rendered":"VHDL-Projekt Datenstruktur und Programme"},"content":{"rendered":"

Ordnerstruktur
\n<\/strong>Synthese<\/em> (oder quartus)
\n. \u00a0\u00a0 – Projektdatei:\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 projekt.qpf
\n. \u00a0\u00a0 – Pinzuweisung: \u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 datei.tcl
\n.\u00a0 \u00a0 \u00a0 [Ordner output_files<\/em>] wird durch Synthese generiert
\n.\u00a0\u00a0\u00a0\u00a0\u00a0 – synthetisiertes File f\u00fcr FPGA:\u00a0\u00a0\u00a0 datei.sof
\n.\u00a0\u00a0\u00a0\u00a0\u00a0 – kompiliertes File f\u00fcr Memory:\u00a0\u00a0 datei.pof
\nVHDL<\/em> (oder source)
\n.\u00a0\u00a0\u00a0 – Es braucht ein Top-Level\u00a0\u00a0 top.xxx (rechte Maus) Rechte zuweisen
\n.\u00a0\u00a0\u00a0 – Schaltpl\u00e4ne: \u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 datei.bdf
\n.\u00a0\u00a0\u00a0 – importierete Bl\u00f6cke (IP): \u00a0 datei.qpf
\n.\u00a0\u00a0\u00a0 – eigene Bl\u00f6cke\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 datei.vhd
\n.\u00a0\u00a0 – testbench:\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 tb_datei.vhd
\nSoftware<\/em>
\n.\u00a0\u00a0\u00a0 – files.c
\n.\u00a0\u00a0\u00a0 – files.h
\nSimulation<\/a><\/em> (oder questasim)
\n. \u00a0 \u00a0\u00a0 Ordner<\/em> questasim<\/em>
\n.\u00a0\u00a0\u00a0\u00a0 \u00a0 \u00a0 \u00a0\u00a0\u00a0 – <\/em>Simulatondatei:\u00a0\u00a0 test_midi.mpf<\/em>
\n.\u00a0\u00a0\u00a0\u00a0\u00a0 \u00a0 \u00a0\u00a0\u00a0\u00a0 – <\/em>Signaldatei:\u00a0 \u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 wave.do
\n<\/em>.\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 [Ordner work]\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 <\/em>wird durch questasim generiert
\n.\u00a0\u00a0\u00a0\u00a0\u00a0 Ordner<\/em> script<\/em> (Verzeichnis zum Aufrufen der Simulation)
\n.\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 – compile.do<\/a>
\n.\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 – test_input.txt<\/a>
\n.\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 – test_output_results.txt<\/p>\n

……………………………………………………………………………………..
\n<\/strong><\/p>\n

FPGA Synthese: Quartus<\/strong>
\nDas Programm Quartus<\/em> von altera (lizenz) ist sehr m\u00e4chtig. Ohne Lizenz, kann die Datei nicht auf das FPGA geladen werden.
\nIn der Synthese werden die Pins zugewisen, die Verbindungen gelegt, das FPGA-Innenleben designt.<\/p>\n

Die Synthese dauert sehr lange. Nach dem Synthetisieren wird der Stream auf das Board oder auf den Flash-Memory geladen.<\/p>\n

home\/bin\/quartus_x.sh<\/pre>\n
 <\/p>\n
Simulation: Questasim<\/strong>
\nDas externe Programm questasim<\/em> ist ein ausf\u00fchrliches Simulationsprogramm.
\nQuartus selbst wird mit Modelsim mitgeliefert, das jedoch begr\u00e4nzt in der Anzahl zu simulierenden Bl\u00f6cke ist.<\/p>\n
Simuliert \u00fcber Testbenches<\/a>, die man \u00fcber die Konsole per Script ausf\u00fchrt<\/a>.<\/p>\n
\u00a0<\/strong><\/p>\n","protected":false},"excerpt":{"rendered":"
Ordnerstruktur Synthese (oder quartus) . \u00a0\u00a0 – Projektdatei:\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 projekt.qpf . \u00a0\u00a0 – Pinzuweisung: \u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 datei.tcl .\u00a0 \u00a0 \u00a0 [Ordner output_files] wird durch Synthese generiert .\u00a0\u00a0\u00a0\u00a0\u00a0 – synthetisiertes File f\u00fcr FPGA:\u00a0\u00a0\u00a0 datei.sof .\u00a0\u00a0\u00a0\u00a0\u00a0 – kompiliertes File f\u00fcr Memory:\u00a0\u00a0 datei.pof VHDL (oder source) .\u00a0\u00a0\u00a0 – Es braucht ein Top-Level\u00a0\u00a0 top.xxx (rechte Maus) Rechte zuweisen .\u00a0\u00a0\u00a0 – Schaltpl\u00e4ne: … VHDL-Projekt Datenstruktur und Programme<\/span> weiterlesen<\/a><\/p>\n","protected":false},"author":1,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":[],"categories":[38,21],"tags":[36,40],"_links":{"self":[{"href":"https:\/\/coolt.ch\/notizen\/wp-json\/wp\/v2\/posts\/151"}],"collection":[{"href":"https:\/\/coolt.ch\/notizen\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/coolt.ch\/notizen\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/coolt.ch\/notizen\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/coolt.ch\/notizen\/wp-json\/wp\/v2\/comments?post=151"}],"version-history":[{"count":15,"href":"https:\/\/coolt.ch\/notizen\/wp-json\/wp\/v2\/posts\/151\/revisions"}],"predecessor-version":[{"id":814,"href":"https:\/\/coolt.ch\/notizen\/wp-json\/wp\/v2\/posts\/151\/revisions\/814"}],"wp:attachment":[{"href":"https:\/\/coolt.ch\/notizen\/wp-json\/wp\/v2\/media?parent=151"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/coolt.ch\/notizen\/wp-json\/wp\/v2\/categories?post=151"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/coolt.ch\/notizen\/wp-json\/wp\/v2\/tags?post=151"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}